This invention relates generally to timing, in particular to reducing run-time in timing analysis.
Integrated circuits comprise many interconnects for connecting blocks of circuitry. As the size of integrated circuits continues to shrink, the number of sources of variation which need to be modeled in order to accurately represent timing behavior has greatly increased. This, in turn, has led to an explosive increase in modeling run-time for integrated circuits.
The tool development community has responded by removing un-needed calculations within a timing run, increasing the use of caching, etc. However, even these efforts have fallen short of reducing run-time to a satisfactory level. Some chips take many days to complete timing analysis on the fastest machines available. This extended analysis time has already delayed the release of some designs into the foundry.
There is thus a need for an improved timing technique with reduced run-time.